The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for a vertical-transport field-effect transistor and methods for forming a structure for a vertical-transport field-effect transistor.
Traditional complementary metal-oxide-semiconductor (CMOS) structures for a field-effect transistor include a source, a drain, a channel situated between the source and drain, and a gate electrode configured to respond to a gate voltage by selectively connecting the source and drain to each other through the channel. Field-effect transistor structures can be broadly categorized based upon the orientation of the channel relative to a surface of a semiconductor substrate associated with their formation.
Planar field-effect transistors and fin-type field-effect transistors constitute a category of transistor structures in which the flow of gated current in the channel is oriented in a horizontal direction parallel to the substrate surface. In a vertical-transport field-effect transistor, the source/drain regions are arranged at the top and bottom of a semiconductor fin or pillar. The direction of the gated current in the channel between the source region and the drain region is oriented generally perpendicular (i.e., vertical) to the substrate surface and parallel to the height of the semiconductor fin or pillar.
The bottom source/drain region of a vertical-transport field-effect transistor is contacted by a contact that extends vertically from above the top source/drain region. The gate electrode must remain isolated from the contact. As the distance between the gate electrode and the contact is downwardly scaled, the ability to reliably maintain the electrical isolation becomes more difficult due to, for example, shifts in the lithography overlay forming the contact opening for the contact. The result of compromised electrical isolation may be an electrical short between the gate electrode and the contact to the bottom source/drain region.